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nickg / nvc / 21567935534
93%

Build:
DEFAULT BRANCH: master
Ran 01 Feb 2026 06:33PM UTC
Jobs 1
Files 102
Run time 1min
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01 Feb 2026 06:23PM UTC coverage: 92.608% (-0.01%) from 92.618%
21567935534

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github

nickg
Proper handling of System Verilog import declarations

Fixes #1387

33 of 48 new or added lines in 3 files covered. (68.75%)

1 existing line in 1 file now uncovered.

76617 of 82733 relevant lines covered (92.61%)

440768.84 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
15
95.71
-0.33% src/vlog/vlog-parse.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
95.71
-0.33% src/vlog/vlog-parse.c
Jobs
ID Job ID Ran Files Coverage
1 21567935534.1 01 Feb 2026 06:33PM UTC 102
92.61
GitHub Action Run
Source Files on build 21567935534
  • Tree
  • List 102
  • Changed 4
  • Source Changed 0
  • Coverage Changed 4
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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