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nickg / nvc / 21567935534 / 1
93%
master: 93%

Build:
DEFAULT BRANCH: master
Ran 01 Feb 2026 06:33PM UTC
Files 102
Run time 3s
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01 Feb 2026 06:23PM UTC coverage: 92.608% (-0.01%) from 92.618%
21567935534.1

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nickg
Proper handling of System Verilog import declarations

Fixes #1387

76617 of 82733 relevant lines covered (92.61%)

440768.84 hits per line

Source Files on job 21567935534.1
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