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nickg / nvc / 20742323211
93%
master: 93%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 06 Jan 2026 08:24AM UTC
Jobs 1
Files 101
Run time 1min
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06 Jan 2026 08:14AM UTC coverage: 92.595% (+0.003%) from 92.592%
20742323211

push

github

nickg
Parse Verilog pulse control specparams

21 of 21 new or added lines in 2 files covered. (100.0%)

67 existing lines in 3 files now uncovered.

75992 of 82069 relevant lines covered (92.6%)

466163.16 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
1
95.19
-0.1% src/lexer.l
2
99.49
0.05% src/vhdl/vhdl-predef.c
64
97.16
0.02% src/lower.c
Jobs
ID Job ID Ran Files Coverage
1 20742323211.1 06 Jan 2026 08:24AM UTC 101
92.6
GitHub Action Run
Source Files on build 20742323211
  • Tree
  • List 101
  • Changed 4
  • Source Changed 0
  • Coverage Changed 4
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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