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nickg / nvc / 20776929426
93%
master: 93%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 07 Jan 2026 09:43AM UTC
Jobs 1
Files 101
Run time 1min
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07 Jan 2026 09:33AM UTC coverage: 92.597% (+0.002%) from 92.595%
20776929426

push

github

nickg
Downgrade Verilog unconnected port diagnostic to a warning

18 of 19 new or added lines in 1 file covered. (94.74%)

20 existing lines in 2 files now uncovered.

75996 of 82072 relevant lines covered (92.6%)

444900.55 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
90.82
0.07% src/elab.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
90.82
0.07% src/elab.c
19
88.76
0.06% src/vlog/vlog-udp.c
Jobs
ID Job ID Ran Files Coverage
1 20776929426.1 07 Jan 2026 09:43AM UTC 101
92.6
GitHub Action Run
Source Files on build 20776929426
  • Tree
  • List 101
  • Changed 2
  • Source Changed 0
  • Coverage Changed 2
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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