nickg / nvc / 18663024254
93%

DEFAULT BRANCH: master
Ran
Jobs 1
Files 100
Run time 1min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst
coverage: 92.569% (-0.01%) from 92.581%
18663024254

push

github

nickg 
Basic code generation for Verilog real variables

69 of 88 new or added lines in 4 files covered. (78.41%)

1 existing line in 1 file now uncovered.

74793 of 80797 relevant lines covered (92.57%)

454599.15 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
6
94.1
 -0.12% src/vlog/vlog-lower.c
6
90.45
 -3.16% src/vpi/vpi-systf.c
7
83.5
 -0.85% src/vpi/vpi-model.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
83.5
 -0.85% src/vpi/vpi-model.c
Jobs
ID Job ID Ran Files Coverage
1 18663024254.1 100
92.57
 GitHub Action Run
Source Files on build 18663024254