nickg / nvc / 17415665085
93%

DEFAULT BRANCH: master
Ran
Jobs 1
Files 99
Run time 1min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst
coverage: 92.625% (+0.001%) from 92.624%
17415665085

push

github

nickg 
Handle Verilog `include directive in preprocessor

150 of 161 new or added lines in 4 files covered. (93.17%)

50 existing lines in 4 files now uncovered.

73035 of 78850 relevant lines covered (92.63%)

590087.71 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
4
94.51
 -1.09% src/vlog/vlog-pp.l
7
88.76
 1.15% src/scan.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
88.76
 1.15% src/scan.c
5
94.16
 0.15% src/vlog/vlog-sem.c
19
82.4
 0.29% src/vlog/vlog-util.c
25
94.98
 0.03% src/elab.c
Jobs
ID Job ID Ran Files Coverage
1 17415665085.1 99
92.63
 GitHub Action Run
Source Files on build 17415665085