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nickg / nvc / 17415665085
93%

Build:
DEFAULT BRANCH: master
Ran 02 Sep 2025 09:03PM UTC
Jobs 1
Files 99
Run time 1min
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02 Sep 2025 08:30PM UTC coverage: 92.625% (+0.001%) from 92.624%
17415665085

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github

nickg
Handle Verilog `include directive in preprocessor

150 of 161 new or added lines in 4 files covered. (93.17%)

50 existing lines in 4 files now uncovered.

73035 of 78850 relevant lines covered (92.63%)

590087.71 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
4
94.51
-1.09% src/vlog/vlog-pp.l
7
88.76
1.15% src/scan.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
88.76
1.15% src/scan.c
5
94.16
0.15% src/vlog/vlog-sem.c
19
82.4
0.29% src/vlog/vlog-util.c
25
94.98
0.03% src/elab.c
Jobs
ID Job ID Ran Files Coverage
1 17415665085.1 02 Sep 2025 09:03PM UTC 99
92.63
GitHub Action Run
Source Files on build 17415665085
  • Tree
  • List 99
  • Changed 7
  • Source Changed 0
  • Coverage Changed 7
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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