nickg / nvc / 17359993468
93%

DEFAULT BRANCH: master
Ran
Jobs 1
Files 99
Run time 1min
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coverage: 92.624% (-0.03%) from 92.65%
17359993468

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github

nickg 
Short-circuiting for Verilog && and || operators

79 of 82 new or added lines in 5 files covered. (96.34%)

78 existing lines in 5 files now uncovered.

72919 of 78726 relevant lines covered (92.62%)

582064.08 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
96.4
 -0.01% src/vlog/vlog-parse.c
2
96.38
 -0.04% src/vlog/vlog-lower.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
96.38
 -0.04% src/vlog/vlog-lower.c
3
90.28
 -0.53% src/thread.c
5
90.12
 -1.03% src/hash.c
24
87.61
 0.0% src/scan.c
45
93.6
 -2.15% src/lexer.l
Jobs
ID Job ID Ran Files Coverage
1 17359993468.1 99
92.62
 GitHub Action Run
Source Files on build 17359993468