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nickg / nvc / 16891751361
93%

Build:
DEFAULT BRANCH: master
Ran 11 Aug 2025 09:00PM UTC
Jobs 1
Files 98
Run time 3min
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11 Aug 2025 08:35PM UTC coverage: 92.564% (+0.02%) from 92.549%
16891751361

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github

nickg
Lowering for Verilog repeat/while loops

54 of 54 new or added lines in 2 files covered. (100.0%)

128 existing lines in 2 files now uncovered.

71998 of 77782 relevant lines covered (92.56%)

562416.58 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
20
96.64
0.13% src/vlog/vlog-lower.c
108
96.29
0.23% src/vlog/vlog-parse.c
Jobs
ID Job ID Ran Files Coverage
1 16891751361.1 11 Aug 2025 09:00PM UTC 98
92.56
GitHub Action Run
Source Files on build 16891751361
  • Tree
  • List 98
  • Changed 4
  • Source Changed 0
  • Coverage Changed 4
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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