nickg / nvc / 10435132666
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 79
Run time 1min
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Rst
coverage: 92.007% (-0.01%) from 92.021%
10435132666

push

github

nickg 
Code generation for Verilog primitive gates

54 of 56 new or added lines in 1 file covered. (96.43%)

151 existing lines in 7 files now uncovered.

58892 of 64008 relevant lines covered (92.01%)

658750.4 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
2
92.76
 -0.1% src/vlog/vlog-lower.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
90.16
 -0.18% src/thread.c
7
75.34
 -1.19% src/server.c
11
86.67
 0.0% src/scan.c
14
96.13
 0.7% src/vlog/vlog-sem.c
36
91.0
 -0.25% src/vlog/vlog-parse.c
36
91.88
 -0.23% src/lexer.l
46
92.76
 -0.1% src/vlog/vlog-lower.c
Jobs
ID Job ID Ran Files Coverage
1 10435132666.1 79
92.01
 GitHub Action Run
Source Files on build 10435132666