nickg / nvc / 10435132666
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 79
Run time 1min
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coverage: 92.007% (-0.01%) from 92.021%
10435132666

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github

nickg 
Code generation for Verilog primitive gates

54 of 56 new or added lines in 1 file covered. (96.43%)

151 existing lines in 7 files now uncovered.

58892 of 64008 relevant lines covered (92.01%)

658750.4 hits per line

Jobs
ID Job ID Ran Files Coverage
1 10435132666.1 0
92.01
 GitHub Action Run
Source Files on build 10435132666
Detailed source file information is not available for this build.