• Home
  • Features
  • Pricing
  • Docs
  • Announcements
  • Sign In

nickg / nvc / 10439661912
92%
master: 92%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 18 Aug 2024 10:03AM UTC
Jobs 1
Files 79
Run time 1min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst

18 Aug 2024 08:38AM UTC coverage: 92.033% (+0.03%) from 92.007%
10439661912

push

github

nickg
Fix precedence for Verilog binary operators

61 of 65 new or added lines in 3 files covered. (93.85%)

58949 of 64052 relevant lines covered (92.03%)

658551.42 hits per line

Jobs
ID Job ID Ran Files Coverage
1 10439661912.1 18 Aug 2024 10:03AM UTC 0
92.03
GitHub Action Run
Source Files on build 10439661912
Detailed source file information is not available for this build.
  • Back to Repo
  • 39a57216 on github
  • Prev Build on test (#10435132666)
  • Next Build on test (#10477855744)
STATUS · Troubleshooting · Open an Issue · Sales · Support · CAREERS · ENTERPRISE · START FREE · SCHEDULE DEMO
ANNOUNCEMENTS · TWITTER · TOS & SLA · Supported CI Services · What's a CI service? · Automated Testing

© 2026 Coveralls, Inc