10644540227

Builds	Branch	Commit	Type	Ran	Committer	Via	Coverage
10644540227	master	Error when inout port has output conversion but no input conversion	push	31 Aug 2024 10:38AM UTC	nickg	github	92.08
10644414980	test	Error when inout port has output conversion but no input conversion	push	31 Aug 2024 10:18AM UTC	nickg	github	92.08
10639249070	master	Crash when dumping waves for array-of-record with non-constant bounds Fixes #962	push	30 Aug 2024 09:25PM UTC	nickg	github	92.08
10638996478	test	Crash when dumping waves for array-of-record with non-constant bounds Fixes xxxx	push	30 Aug 2024 09:00PM UTC	nickg	github	92.09
10638393744	master	Type of range bounds was determined incorrectly. Fixes #961	push	30 Aug 2024 08:03PM UTC	nickg	github	92.09
10638242423	test	Type of range bounds was determined incorrectly. Fixes xxx	push	30 Aug 2024 07:47PM UTC	nickg	github	92.08
10622040110	master	Fix crash when 'stable is used with record type. Fixes #960	push	29 Aug 2024 08:28PM UTC	nickg	github	92.08
10621854661	test	Fix crash when 'stable is used with record type. Fixes xxx	push	29 Aug 2024 08:14PM UTC	nickg	github	92.08
10605214793	master	Dump downto arrays-of-arrays in the correct order. Fixes #957	push	28 Aug 2024 10:26PM UTC	nickg	github	92.08
10605052542	test	Dump downto arrays-of-arrays in the correct order. Fixes xxxx	push	28 Aug 2024 10:12PM UTC	nickg	github	92.07
10584373214	master	Check PSL properties are in simple subset	push	27 Aug 2024 07:21PM UTC	nickg	github	92.08
10584189837	test	Check PSL properties are in simple subset	push	27 Aug 2024 07:08PM UTC	nickg	github	92.08
10539989592	master	Various fixes for Verilog module instantiation. Issue #937	push	24 Aug 2024 04:47PM UTC	nickg	github	92.05
10539916391	test	Various fixes for Verilog module instantiation. Issue xxx	push	24 Aug 2024 04:34PM UTC	nickg	github	92.05
10535953566	master	Sync NEWS.md from 1.13 branch	push	24 Aug 2024 05:18AM UTC	nickg	github	92.05

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