nickg / nvc / 10539916391
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 79
Run time 10min
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coverage: 92.048% (-0.008%) from 92.056%
10539916391

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github

nickg 
Various fixes for Verilog module instantiation. Issue xxx

24 of 34 new or added lines in 4 files covered. (70.59%)

94 existing lines in 1 file now uncovered.

58946 of 64038 relevant lines covered (92.05%)

658919.03 hits per line

Jobs
ID Job ID Ran Files Coverage
1 10539916391.1 0
92.05
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Source Files on build 10539916391
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