nickg / nvc / 10539989592
92%

DEFAULT BRANCH: master
Ran
Jobs 1
Files 79
Run time 2min
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coverage: 92.047% (+0.001%) from 92.046%
10539989592

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github

nickg 
Various fixes for Verilog module instantiation. Issue #937

24 of 34 new or added lines in 4 files covered. (70.59%)

95 existing lines in 2 files now uncovered.

58945 of 64038 relevant lines covered (92.05%)

660936.66 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
95.03
 0.14% src/elab.c
1
97.34
 0.0% src/lower.c
1
89.18
 -0.15% src/rt/wave.c
7
92.84
 -0.73% src/vlog/vlog-lower.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
90.16
 -0.18% src/thread.c
94
73.09
 -0.12% src/util.c
Jobs
ID Job ID Ran Files Coverage
1 10539989592.1 79
92.05
 GitHub Action Run
Source Files on build 10539989592