nickg / nvc / 10539989592
92%

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Files 79
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coverage: 92.047% (+0.001%) from 92.046%
10539989592

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nickg 
Various fixes for Verilog module instantiation. Issue #937

24 of 34 new or added lines in 4 files covered. (70.59%)

95 existing lines in 2 files now uncovered.

58945 of 64038 relevant lines covered (92.05%)

660936.66 hits per line

Jobs
ID Job ID Ran Files Coverage
1 10539989592.1 0
92.05
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