nickg / nvc / 18632896339

Builds Branch Commit Type Ran Committer Via Coverage
18632896339 test Constant fold Verilog binary and/or/xor push nickg github
92.58
18632717154 test Constant fold Verilog binary and/or/xor push nickg github
92.58
18629953402 master Correct result width for $random push nickg github
92.58
18629683662 test Correct result width for $random push nickg github
92.58
18613682687 v1.18-branch Bump version to 1.18.1 push nickg github
92.65
18613541779 v1.18-branch Switch to macos-15-intel label for X86 macOS tests push nickg github
92.65
18613466257 test Switch to macos-15-intel label for X86 macOS tests push nickg github
92.56
18553724322 master Fix incorrect string concatenation simplification Fixes #1323 push nickg github
92.56
18553251982 test Fix incorrect string concatenation simplification push nickg github
92.56
18476552328 master Parse string variable declarations in modules push nickg github
92.56
18475654093 test Parse string variable declarations in modules push nickg github
92.56
18428170938 master Better handling of System Verilog nulls push nickg github
92.55
18427927468 test Better handling of System Verilog nulls push nickg github
92.55
18400212175 master Remove the precompile elaboration mode push nickg github
92.55
18400004699 test Remove the precompile elaboration mode push nickg github
92.55