nickg / nvc / 18427927468
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 100
Run time 1min
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Rst
coverage: 92.549% (-0.002%) from 92.551%
18427927468

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github

nickg 
Better handling of System Verilog nulls

40 of 44 new or added lines in 4 files covered. (90.91%)

2 existing lines in 2 files now uncovered.

74468 of 80463 relevant lines covered (92.55%)

439309.04 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
96.46
 -0.02% src/vlog/vlog-sem.c
3
81.38
 -1.72% src/vlog/vlog-util.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
94.27
 0.01% src/vlog/vlog-lower.c
1
96.46
 -0.02% src/vlog/vlog-sem.c
Jobs
ID Job ID Ran Files Coverage
1 18427927468.1 100
92.55
 GitHub Action Run
Source Files on build 18427927468