nickg / nvc / 16669709596

Builds Branch Commit Type Ran Committer Via Coverage
16669709596 test Implement Verilog casex push nickg github
92.4
16656920975 test Implement Verilog and-reduction push nickg github
92.41
16632643923 test Add mixed_cic to regression tests push nickg github
92.4
16629796914 master Adjust scheduling for Verilog blocking assignment Fixes #1227 push nickg github
92.41
16629538395 test Adjust scheduling for Verilog blocking assignment push nickg github
92.42
16590906316 master Check whether Quartus paths exist in new directory layout also push nickg github
92.4
16590738223 master Check for missing files in the Quartus install script Fixes #1252 push nickg github
92.4
16579071870 master Parse Verilog disable statements push nickg github
92.4
16578878807 test Parse Verilog disable statements push nickg github
92.4
16554826086 master Rename global event callbacks to phase callbacks push nickg github
92.4
16552692117 test Rename global event callbacks to phase callbacks push nickg github
92.4
16538025326 v1.17-branch Update for 1.17.1 release push nickg github
92.34
16537719063 v1.17-branch Improve test for issue #1249 push nickg github
92.34
16530753816 master Parse Verilog procedural continuous assignments push nickg github
92.38
16530067250 test Parse Verilog procedural continuous assignments push nickg github
92.38