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Ran 25 Oct 2019 06:47PM UTC

Files 64

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Committed 25 Oct 2019 06:31PM UTC coverage: 74.565% (+0.04%) from 74.53%

Job # 2176.1

Build Type

Pull #462

travis-ci

Committed by

web-flow

Commit Message

Revert "Switch to mainline pyverilog"

This reverts commit 5d3125fb0.

This commit adds back requirements.txt so we can point to our forked
version of pyverilog.

Pull Request Pull Request #462: Parse n-d array types in verilog ports

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