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nickg / nvc / 25520612010 / 1
92%
master: 92%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 07 May 2026 08:47PM UTC
Files 103
Run time 9s
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07 May 2026 08:34PM UTC coverage: 92.256% (+0.005%) from 92.251%
25520612010.1

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Constant folding for Verilog << and >>>

77638 of 84155 relevant lines covered (92.26%)

641771.84 hits per line

Source Files on job 25520612010.1
  • Tree
  • List 103
  • Changed 5
  • Source Changed 0
  • Coverage Changed 5
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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