nickg / nvc / 25520612010
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 103
Run time 1min
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Rst
coverage: 92.256% (+0.005%) from 92.251%
25520612010

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github

nickg 
Constant folding for Verilog << and >>>

70 of 77 new or added lines in 2 files covered. (90.91%)

109 existing lines in 3 files now uncovered.

77638 of 84155 relevant lines covered (92.26%)

641771.84 hits per line

Uncovered Changes

Lines Coverage ∆ File
7
92.82
 -0.22% src/vlog/vlog-number.c

Coverage Regressions

Lines Coverage ∆ File
91
95.63
 0.14% src/vlog/vlog-parse.c
15
93.85
 0.01% src/vlog/vlog-lower.c
3
92.82
 -0.22% src/vlog/vlog-number.c
Jobs
ID Job ID Ran Files Coverage
1 25520612010.1 103
92.26
 GitHub Action Run
Source Files on build 25520612010