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nickg / nvc / 25340237924 / 1
92%
master: 92%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 04 May 2026 08:08PM UTC
Files 103
Run time 7s
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04 May 2026 07:55PM UTC coverage: 92.232% (-0.001%) from 92.233%
25340237924.1

Pull #1513

github

web-flow
Merge fb04cd3be into 06f24f88d
Pull Request #1513: Verilog: Support default values on macro functions

77520 of 84049 relevant lines covered (92.23%)

628607.54 hits per line

Source Files on job 25340237924.1
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  • Changed 3
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