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nickg / nvc / 25340237924
92%
master: 92%

Build:
Build:
LAST BUILD BRANCH: issue-1522
DEFAULT BRANCH: master
Ran 04 May 2026 08:08PM UTC
Jobs 1
Files 103
Run time 1min
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04 May 2026 07:55PM UTC coverage: 92.232% (-0.001%) from 92.233%
25340237924

Pull #1513

github

web-flow
Merge fb04cd3be into 06f24f88d
Pull Request #1513: Verilog: Support default values on macro functions

6 of 6 new or added lines in 1 file covered. (100.0%)

2 existing lines in 1 file now uncovered.

77520 of 84049 relevant lines covered (92.23%)

628607.54 hits per line

Coverage Regressions

Lines Coverage ∆ File
2
88.71
-0.41% src/hash.c
Jobs
ID Job ID Ran Files Coverage
1 25340237924.1 04 May 2026 08:08PM UTC 103
92.23
GitHub Action Run
Source Files on build 25340237924
  • Tree
  • List 103
  • Changed 3
  • Source Changed 0
  • Coverage Changed 3
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
  • Back to Repo
  • Pull Request #1513
  • PR Base - master (#25328287287)
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