nickg / nvc / 24927520513 / 1
92%
master: 92%

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coverage: 92.199% (-0.007%) from 92.206%
24927520513.1

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nickg 
Avoid division by zero when simplifying Verilog expression

77119 of 83644 relevant lines covered (92.2%)

589801.81 hits per line

Source Files on job 24927520513.1