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nickg / nvc / 24927520513
92%

Build:
DEFAULT BRANCH: master
Ran 25 Apr 2026 09:24AM UTC
Jobs 1
Files 103
Run time 1min
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25 Apr 2026 08:55AM UTC coverage: 92.199% (-0.007%) from 92.206%
24927520513

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github

nickg
Avoid division by zero when simplifying Verilog expression

2 of 2 new or added lines in 1 file covered. (100.0%)

32 existing lines in 4 files now uncovered.

77119 of 83644 relevant lines covered (92.2%)

589801.81 hits per line

Coverage Regressions

Lines Coverage ∆ File
23
87.98
-3.42% src/vpi/vpi-systf.c
4
69.23
2.2% src/vpi/vpi-util.c
3
92.33
0.0% src/printf.c
2
91.65
0.0% src/vlog/vlog-simp.c
Jobs
ID Job ID Ran Files Coverage
1 24927520513.1 25 Apr 2026 09:24AM UTC 103
92.2
GitHub Action Run
Source Files on build 24927520513
  • Tree
  • List 103
  • Changed 6
  • Source Changed 0
  • Coverage Changed 6
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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