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92%
master: 92%

Ran 12 Mar 2026 08:37AM UTC

Files 102

Run time 7s

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Committed 12 Mar 2026 08:27AM UTC coverage: 92.481% (-0.01%) from 92.494%

Job # 22993020506.1

Build Type

push

github

Committed by

web-flow

Commit Message

Add missing V_FOR_LOOP in build_sensitivity for Verilog always blocks (#1451)

* Add missing V_FOR_LOOP in build_sensitivity for Verilog always blocks

* Add checks for init/test/step expressions in for loops

Coverage Stats

77782 of 84106 relevant lines covered (92.48%)

434075.59 hits per line

nickg / nvc / 22993020506 / 1
92%
master: 92%

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nickg / nvc / 22993020506 / 1 92% master: 92%

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92%
master: 92%

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