nickg / nvc / 22993020506
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Jobs 1
Files 102
Run time 1min
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coverage: 92.481% (-0.01%) from 92.494%
22993020506

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Add missing V_FOR_LOOP in build_sensitivity for Verilog always blocks (#1451)

* Add missing V_FOR_LOOP in build_sensitivity for Verilog always blocks

* Add checks for init/test/step expressions in for loops

0 of 12 new or added lines in 1 file covered. (0.0%)

77782 of 84106 relevant lines covered (92.48%)

434075.59 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
12
93.14
 -3.31% src/vlog/vlog-simp.c
Jobs
ID Job ID Ran Files Coverage
1 22993020506.1 102
92.48
 GitHub Action Run
Source Files on build 22993020506