nickg / nvc / 22971844628 / 1
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
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coverage: 92.456% (-0.01%) from 92.467%
22971844628.1

Pull #1451

github

web-flow 
Merge e99dd8c73 into e70be7f3e
Pull Request #1451: Add missing V_FOR_LOOP in build_sensitivity for Verilog always blocks

77786 of 84133 relevant lines covered (92.46%)

434501.01 hits per line

Source Files on job 22971844628.1