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nickg / nvc / 22971844628
92%
master: 92%

Build:
Build:
LAST BUILD BRANCH: range-records
DEFAULT BRANCH: master
Ran 11 Mar 2026 09:05PM UTC
Jobs 1
Files 102
Run time 1min
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11 Mar 2026 07:59PM UTC coverage: 92.456% (-0.01%) from 92.467%
22971844628

Pull #1451

github

web-flow
Merge e99dd8c73 into e70be7f3e
Pull Request #1451: Add missing V_FOR_LOOP in build_sensitivity for Verilog always blocks

0 of 12 new or added lines in 1 file covered. (0.0%)

77786 of 84133 relevant lines covered (92.46%)

434501.01 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
12
93.14
-3.31% src/vlog/vlog-simp.c
Jobs
ID Job ID Ran Files Coverage
1 22971844628.1 11 Mar 2026 09:05PM UTC 102
92.46
GitHub Action Run
Source Files on build 22971844628
  • Tree
  • List 102
  • Changed 2
  • Source Changed 0
  • Coverage Changed 2
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
  • Back to Repo
  • Pull Request #1451
  • PR Base - master (#22894664511)
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