nickg / nvc / 22824402361 / 1
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Files 102
Run time 3s
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coverage: 92.495% (+0.01%) from 92.481%
22824402361.1

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nickg 
Handle cycles in Verilog nets

77659 of 83960 relevant lines covered (92.5%)

443552.33 hits per line

Source Files on job 22824402361.1