nickg / nvc / 22824402361
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 102
Run time 1min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst
coverage: 92.495% (+0.01%) from 92.481%
22824402361

push

github

nickg 
Handle cycles in Verilog nets

35 of 36 new or added lines in 1 file covered. (97.22%)

28 existing lines in 2 files now uncovered.

77659 of 83960 relevant lines covered (92.5%)

443552.33 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
96.84
 0.02% src/rt/model.c

Uncovered Existing Lines

Lines Coverage ∆ File
2
88.71
 -0.41% src/hash.c
26
96.84
 0.02% src/rt/model.c
Jobs
ID Job ID Ran Files Coverage
1 22824402361.1 102
92.5
 GitHub Action Run
Source Files on build 22824402361