nickg / nvc / 19398843256 / 1
93%
master: 93%

LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran
Files 100
Run time 3s
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coverage: 92.57% (-0.001%) from 92.571%
19398843256.1

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github

nickg 
Refactor lowering of Verilog selects

74842 of 80849 relevant lines covered (92.57%)

461099.79 hits per line

Source Files on job 19398843256.1