nickg / nvc / 16672560352 / 1
93%
master: 93%

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Files 99
Run time 206min
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coverage: 92.402% (-0.004%) from 92.406%
16672560352.1

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nickg 
Implement Verilog casex

72189 of 78125 relevant lines covered (92.4%)

551503.13 hits per line

Source Files on job 16672560352.1