nickg / nvc / 16672560352
93%

DEFAULT BRANCH: master
Ran
Jobs 1
Files 99
Run time 217min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst
coverage: 92.402% (-0.004%) from 92.406%
16672560352

push

github

nickg 
Implement Verilog casex

12 of 21 new or added lines in 4 files covered. (57.14%)

37 existing lines in 3 files now uncovered.

72189 of 78125 relevant lines covered (92.4%)

551503.13 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
4
35.14
 -1.48% src/vpi/vpi-util.c
5
86.21
 -3.88% src/vpi/vpi-systf.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
35.14
 -1.48% src/vpi/vpi-util.c
13
97.31
 0.01% src/jit/jit-irgen.c
23
96.95
 0.18% src/vlog/vlog-lower.c
Jobs
ID Job ID Ran Files Coverage
1 16672560352.1 99
92.4
 GitHub Action Run
Source Files on build 16672560352