nickg / nvc / 16006985729 / 1
93%
master: 93%

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DEFAULT BRANCH: master
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Run time 8s
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coverage: 92.26% (+0.009%) from 92.251%
16006985729.1

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nickg 
Map VHDL generics to Verilog parameters

70636 of 76562 relevant lines covered (92.26%)

561717.81 hits per line

Source Files on job 16006985729.1