SystemRDL / PeakRDL-regblock-vhdl / 14763659860 / 1

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main: 93%

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github

Port synthesis tests to VHDL (#18)

* update synthesis test runners for VHDL
* don't use avalon intf pkg for flattened interface

757 of 884 branches covered (85.63%)

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2845 of 3033 relevant lines covered (93.8%)

5.63 hits per line