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SystemRDL / PeakRDL-regblock-vhdl / 14763659860
92%

Build:
DEFAULT BRANCH: main
Ran 30 Apr 2025 08:24PM UTC
Jobs 1
Files 43
Run time 2min
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30 Apr 2025 08:23PM UTC coverage: 91.958% (+0.002%) from 91.956%
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Port synthesis tests to VHDL (#18)

* update synthesis test runners for VHDL
* don't use avalon intf pkg for flattened interface

757 of 884 branches covered (85.63%)

Branch coverage included in aggregate %.

2845 of 3033 relevant lines covered (93.8%)

5.63 hits per line

Jobs
ID Job ID Ran Files Coverage
1 14763659860.1 30 Apr 2025 08:25PM UTC 43
91.96
GitHub Action Run
Source Files on build 14763659860
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  • List 43
  • Changed 2
  • Source Changed 0
  • Coverage Changed 2
Coverage ∆ File Lines Relevant Covered Missed Hits/Line Branch Hits Branch Misses
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