nickg / nvc / 8807639843 / 1
93%
master: 93%

LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran
Files 79
Run time 3s
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coverage: 91.681% (+0.003%) from 91.678%
8807639843.1

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github

nickg 
Verilog "forever" loops

53561 of 58421 relevant lines covered (91.68%)

656799.98 hits per line

Source Files on job 8807639843.1