nickg / nvc / 6474022552 / 1
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Files 69
Run time 3s
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coverage: 91.136% (-0.03%) from 91.161%
6474022552.1

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nickg 
Verilog continuous assignment and binary "&"

48876 of 53630 relevant lines covered (91.14%)

584505.86 hits per line

Source Files on job 6474022552.1