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nickg / nvc / 6474022552
93%
master: 93%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 10 Oct 2023 07:55PM UTC
Jobs 1
Files 69
Run time 4s
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10 Oct 2023 07:38PM UTC coverage: 91.136% (-0.03%) from 91.161%
6474022552

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github

nickg
Verilog continuous assignment and binary "&"

41 of 41 new or added lines in 2 files covered. (100.0%)

48876 of 53630 relevant lines covered (91.14%)

584505.86 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
4
95.47
-0.51% src/vlog/vlog-lower.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
91.81
0.01% src/jit/jit-x86.c
3
95.47
-0.51% src/vlog/vlog-lower.c
4
97.84
0.0% src/vlog/vlog-node.c
5
96.26
3.72% src/vlog/vlog-sem.c
8
95.79
2.29% src/vlog/vlog-parse.y
11
87.5
0.72% src/vlog/vlog-dump.c
67
71.97
-8.03% src/jit/jit-code.c
Jobs
ID Job ID Ran Files Coverage
1 6474022552.1 10 Oct 2023 07:55PM UTC 69
91.14
GitHub Action Run
Source Files on build 6474022552
  • Tree
  • List 69
  • Changed 53
  • Source Changed 0
  • Coverage Changed 8
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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