SystemRDL / systemrdl-compiler
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LAST BUILD ON BRANCH dev/verilog-preprocessor
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amykyta3 
Implement Verilog Preprocessor. Reworked source reference insfrastructure. #41

Add type hints to some visitors.
Fixed error message bug
Verilog preprocessor unit tests

1152 of 1374 branches covered (83.84%)

Branch coverage included in aggregate %.

4508 of 4786 relevant lines covered (94.19%)

4.7 hits per line

Relevant lines Covered
4786 RELEVANT LINES 4508 COVERED LINES
4.7 HITS PER LINE
Source Files on dev/verilog-preprocessor

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Builds Branch Commit Type Ran Committer Via Coverage
322 dev/verilog-preprocessor Implement Verilog Preprocessor. Reworked source reference insfrastructure. #41 Add type hints to some visitors. Fixed error message bug Verilog preprocessor unit tests push amykyta3 travis-ci pending completion  
320 dev/verilog-preprocessor Verilog preprocessor unit tests push amykyta3 travis-ci pending completion  
319 dev/verilog-preprocessor Verilog preprocessor unit tests push amykyta3 travis-ci pending completion  
318 dev/verilog-preprocessor Add type hints to some visitors. Fixed error message bug push amykyta3 travis-ci pending completion  
317 dev/verilog-preprocessor Implement Verilog Preprocessor. Reworked source reference insfrastructure. #41 push amykyta3 travis-ci pending completion  
316 dev/verilog-preprocessor Rework source reference insfrastructure push amykyta3 travis-ci pending completion  
315 dev/verilog-preprocessor Enable branch coverage. More testcases push amykyta3 travis-ci pending completion  
300 dev/verilog-preprocessor Switch Node.get_rel_path() to use deque during path calculation push amykyta3 travis-ci pending completion  
298 dev/verilog-preprocessor Reorganize perl preprocessor to make room for full verilog preprocessor. #41 push amykyta3 travis-ci pending completion  
286 dev/verilog-preprocessor Reorganize perl preprocessor to make room for full verilog preprocessor. #41 push amykyta3 travis-ci pending completion  
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