317
92%
main: 92%

Ran 09 Sep 2020 05:35AM UTC

Jobs 5

Files 33

Run time 32s

Badge

Build # 317

Build Type

push

travis-ci

Committed by

Commit Message

Implement Verilog Preprocessor. Reworked source reference insfrastructure. #41

Run Details

1064 of 1376 branches covered (77.33%)

Branch coverage included in aggregate %.

4253 of 4770 relevant lines covered (89.16%)

4.45 hits per line

ID	Job ID	Ran	Files	Coverage
1	*317.1 (CIBW_SKIP="cp27- macosx_10_6" SYSTEMRDL_REQUIRE_BINARY_BUILD=)**	09 Sep 2020 05:35AM UTC	33	86.45	Travis Job 317.1
2	*317.2 (CIBW_SKIP="cp27- macosx_10_6" SYSTEMRDL_REQUIRE_BINARY_BUILD=)**	09 Sep 2020 05:35AM UTC	33	86.43	Travis Job 317.2
3	*317.3 (CIBW_SKIP="cp27- macosx_10_6" SYSTEMRDL_REQUIRE_BINARY_BUILD=)**	09 Sep 2020 05:35AM UTC	33	86.43	Travis Job 317.3
4	*317.4 (CIBW_SKIP="cp27- macosx_10_6" SYSTEMRDL_REQUIRE_BINARY_BUILD=)**	09 Sep 2020 05:35AM UTC	33	86.43	Travis Job 317.4
5	*317.5 (CIBW_SKIP="cp27- macosx_10_6" SYSTEMRDL_REQUIRE_BINARY_BUILD=)**	09 Sep 2020 05:35AM UTC	33	86.45	Travis Job 317.5