319
92%
main: 95%

Ran 11 Sep 2020 04:48AM UTC

Jobs 5

Files 33

Run time 23s

Badge

Build # 319

Build Type

push

travis-ci

Committed by

Commit Message

Verilog preprocessor unit tests

Run Details

1154 of 1376 branches covered (83.87%)

Branch coverage included in aggregate %.

4501 of 4778 relevant lines covered (94.2%)

4.71 hits per line

Lines	Coverage	∆	File
3	93.19	-0.52%	/home/travis/build/SystemRDL/systemrdl-compiler/systemrdl/preprocessor/perl_preprocessor.py
3	96.93	72.15%	/home/travis/build/SystemRDL/systemrdl-compiler/systemrdl/preprocessor/verilog_preprocessor.py

ID	Job ID	Ran	Files	Coverage
1	*319.1 (CIBW_SKIP="cp27- macosx_10_6" SYSTEMRDL_REQUIRE_BINARY_BUILD=)**	11 Sep 2020 04:48AM UTC	33	91.83	Travis Job 319.1
2	*319.2 (CIBW_SKIP="cp27- macosx_10_6" SYSTEMRDL_REQUIRE_BINARY_BUILD=)**	11 Sep 2020 04:48AM UTC	33	91.81	Travis Job 319.2
3	*319.3 (CIBW_SKIP="cp27- macosx_10_6" SYSTEMRDL_REQUIRE_BINARY_BUILD=)**	11 Sep 2020 04:48AM UTC	33	91.81	Travis Job 319.3
4	*319.4 (CIBW_SKIP="cp27- macosx_10_6" SYSTEMRDL_REQUIRE_BINARY_BUILD=)**	11 Sep 2020 04:48AM UTC	33	91.81	Travis Job 319.4
5	*319.5 (CIBW_SKIP="cp27- macosx_10_6" SYSTEMRDL_REQUIRE_BINARY_BUILD=)**	11 Sep 2020 04:48AM UTC	33	91.81	Travis Job 319.5