20513114033
92%

Ran 26 Dec 2025 12:35AM UTC

Jobs 1

Files 46

Run time 1min

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Committed 26 Dec 2025 12:34AM UTC coverage: 92.188% (-0.1%) from 92.287%

Build Type

push

github

Committed by

Commit Message

fix external block address width bug (#29)

External regblock addr signals are now always a std_logic_vector,
even when the width is 1.

Run Details

828 of 960 branches covered (86.25%)

Branch coverage included in aggregate %.

3031 of 3226 relevant lines covered (93.96%)

6.58 hits per line

Lines	Coverage	∆	File
3	90.44	-3.05%	/home/runner/work/PeakRDL-regblock-vhdl/PeakRDL-regblock-vhdl/src/peakrdl_regblock_vhdl/utils.py

ID	Job ID	Ran	Files	Coverage
1	20513114033.1	26 Dec 2025 12:36AM UTC	46	92.19	GitHub Action Run