SystemRDL / PeakRDL-regblock-vhdl
92%
main: 92%

LAST BUILD BRANCH: v1.1.1.0+vhdl
DEFAULT BRANCH: main
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coverage: 91.952% (-0.006%) from 91.958%
14764676637

Pull #19

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darsor 
trigger coveralls build
Pull Request #19: VHDL updates for readthedocs documentation

757 of 884 branches covered (85.63%)

Branch coverage included in aggregate %.

2842 of 3030 relevant lines covered (93.8%)

5.63 hits per line

Relevant lines Covered
3030 RELEVANT LINES 2842 COVERED LINES
5.63 HITS PER LINE
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Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
14764676637 dev/update-docs trigger coveralls build Pull #19 darsor github
91.95
14764452579 dev/update-docs added note in quick start about hdl-src/ files Pull #19 darsor github
91.96
14764045636 dev/update-docs trigger documentation build Pull #19 darsor github
91.95
14763906309 dev/update-docs Merge 8e833c163 into 65931089b Pull #19 web-flow github
91.96
14763608932 dev/update-docs updated many missed references to systemverilog exporter push darsor github
91.96
14748011570 dev/update-docs updated cpuif and props docs push darsor github
91.95
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