StanfordAHA / garnet

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LAST BUILD ON BRANCH mem-core-features

branch: mem-core-features

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• mem-core-features
• rename-mem
• update-stub
• master
• refactor-regression-test
• directed-test-global-controller
• mem-functional-model
• top-python
• refactor-regression-tests
• memory-core-linebuffer-mode
• switch-box-directed-test-2
• add-deprecated-decorator
• update-run-verilog-sim
• improved_gc_tb
• gc_functional_model
• update-config-register-gold
• analog_reg_removal_gc
• simple-cgra-v2
• update-bv-int-vector
• switch-box-functional-model
• update-config-register
• update-gold
• simple_pe
• add_IOs
• patch-cosa-install-intructions
• configurable-simple-pe
• hotfix-test_simple_pe-1
• wrap-pe
• fix-parsed-verilog-output
• fix_gc_coverage
• add_read_data
• simple-cgra
• init-py37
• patch-cb-regression
• add-type-maps
• simple-cgra-type_map-fix
• simple-cgra-mux-tests
• master-pin-cosa
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• simple-cgra-fix-pe-core
• simple-cgra-test-zext-wrapper
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• add-config-enable
• test-tile
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• update-cosa
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• hotfix-coreir
• patch-install
• pypi-magma-mantle
• tapeout
• mem_core_connections
• mem_generator
• fix-gold
• global-signal-column
• nb_dev1
• powerdomains
• add-registers
• interconnect-abstractions
• fix_ncsim_err
• fix-mux-wrapper
• iopad
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• interconnect_config
• interconnect-v2
• interconnect-v3
• test-plan
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• powerdomains-2
• interconnect-rename
• update_global_controller_genesis
• interconnect-top
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• interconnect-feature
• from-verilog-fix
• add-aoi-mux
• rm-filecmp
• interconnect-io
• interconnect-pnr
• pd-feature
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• install_test
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• migrate-gemstone-canal
• loosen-dependent-versions
• interconnect-canal
• cannal-io
• canal-features
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• tapeout-pd
• magma-syntax-fix
• halide-flow
• test-tests
• patch-magma-print-output
• leonardt-patch-1
• switch-canal
• update-requirements
• global_buffer
• cleanup_travis
• memory_core_impl
• archipelago
• readme_and_cleanup
• new_io
• pd-rtl
• simple_mapper
• pnr_info
• new_global_wiring
• io_core
• unified_cgra
• fix-global-buffer-errors
• late-bind-peak-rtl
• fix-gc-op-select
• global_controller_axi
• cache_genesis
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• hotfix_remote
• refactor_mapper
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• test_master
• hotfix-glb_param
• mapper
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• glb_impl
• memory_core_db
• refactor_bitstream
• reg_passes
• pe_ordering

Build # 1040

Build Type

Pull #177

travis-ci

Committed by web-flow

Commit Message

Create read_data port for each SRAM feature

Pull Request Pull Request #177: Create read_data port for each SRAM feature

Run Details

2212 of 2316 relevant lines covered (95.51%)

0.96 hits per line