StanfordAHA / garnet

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LAST BUILD ON BRANCH mem-core-features

branch: mem-core-features

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• mem-core-features
• active_high_reset_pe
• add-aoi-mux
• add-config-enable
• add-deprecated-decorator
• add-registers
• add-type-maps
• add_IOs
• add_read_data
• analog_reg_removal_gc
• archipelago
• cache_genesis
• canal-features
• cannal-io
• cleanup_travis
• configurable-simple-pe
• directed-test-global-controller
• dummy-core-instance-names
• fix-gc-op-select
• fix-global-buffer-errors
• fix-gold
• fix-mux-wrapper
• fix-parsed-verilog-output
• fix_gc_coverage
• fix_ncsim_err
• fix_tests
• from-verilog-fix
• gc_functional_model
• glb_impl
• global-signal-column
• global_buffer
• global_controller_axi
• halide-flow
• hotfix-coreir
• hotfix-glb_param
• hotfix-pycodestyle
• hotfix-test_simple_pe-1
• hotfix_remote
• improved_gc_tb
• init-py37
• install_test
• interconnect-abstractions
• interconnect-canal
• interconnect-feature
• interconnect-global-signal
• interconnect-io
• interconnect-pipeline
• interconnect-pnr
• interconnect-rename
• interconnect-test
• interconnect-top
• interconnect-v2
• interconnect-v3
• interconnect-verify
• interconnect_config
• io_core
• iopad
• late-bind-peak-rtl
• leonardt-patch-1
• loosen-dependent-versions
• magma-syntax-fix
• mapper
• master
• master-add-pe-async-reset
• master-pin-cosa
• mem-functional-model
• mem_core_connections
• mem_generator
• memory-core-linebuffer-mode
• memory_core_db
• memory_core_impl
• migrate-gemstone-canal
• nb_dev1
• new_global_wiring
• new_io
• old-pe-tests
• patch-cb-regression
• patch-cosa-install-intructions
• patch-install
• patch-magma-print-output
• pd-feature
• pd-passes
• pd-rtl
• pd_pass_or
• pe_cache
• pe_ordering
• pnr_info
• powerdomains
• powerdomains-2
• pycodestyle
• pypi-magma-mantle
• readme_and_cleanup
• refactor-regression-test
• refactor-regression-tests
• refactor_bitstream
• refactor_mapper
• reg_passes
• rename-mem
• repair_tests
• reset_test
• rm-filecmp
• simple-cgra
• simple-cgra-fix-pe-core
• simple-cgra-mux-tests
• simple-cgra-sb-tests
• simple-cgra-test-zext-wrapper
• simple-cgra-type_map-fix
• simple-cgra-v2
• simple_mapper
• simple_pe
• switch-box-directed-test-2
• switch-box-functional-model
• switch-canal
• tapeout
• tapeout-pd
• test-plan
• test-tests
• test-tile
• test_master
• test_pytest
• top-python
• unified_cgra
• update-bv-int-vector
• update-config-register
• update-config-register-gold
• update-cosa
• update-gold
• update-requirements
• update-run-verilog-sim
• update-simple-cb-test
• update-stub
• update_global_controller_genesis
• wrap-pe
• z3

Build # 1040

Build Type

Pull #177

travis-ci

Committed by web-flow

Commit Message

Create read_data port for each SRAM feature

Pull Request Pull Request #177: Create read_data port for each SRAM feature

Run Details

2212 of 2316 relevant lines covered (95.51%)

0.96 hits per line