dangernoodle-io / pogopin / 29112811310
88%

DEFAULT BRANCH: main
Ran
Jobs 1
Files 38
Run time 1min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst
coverage: 86.512% (+0.1%) from 86.403%
29112811310

push

github

web-flow 
feat: multi-chip mock (esp32/c3/s3) with security-info detection (#53)

- add ESP32, ESP32-C3, ESP32-S3 chipProfiles alongside the existing S2 one
  (chip.go), with register/magic values verified against espflasher's
  gpio.go and target_esp32*.go
- make GET_SECURITY_INFO (opcode 0x14) chip-conditional: S2/ESP32 keep the
  error-status response (magic-detected), C3/S3 return a real 20-byte
  payload carrying ChipID (5/9), matching espflasher's ImageChipID-based
  detection path
- refactor install.go from a single hardcoded S2 port to a port-name ->
  chipProfile map (profileByPort); unknown port names fail loud instead of
  falling back to S2
- add ChipFamily/MockPort/SecurityChipID/ReservedPin to hwbench's
  boardProfile so board-key -> mock-port/chip-quirks live in one place, and
  route ACC_POGOPIN_BOARD to the matching mock port instead of always
  connecting to S2
- add a security-info scenario to the mock bench asserting chip_id for
  chip-ID-detected boards
- fix the c3 board profile's LEDPin/ReservedPin, which were silently wrong
  (15 is flash-reserved and GPIO0 isn't a strap pin on C3) because board
  routing always talked to the S2 mock regardless of board key until now
- add untagged unit tests driving real espflasher against each new profile
  (ChipName, GPIO round trip, security-info detection) plus table tests for
  the security payload layout and the profileByPort map

Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>

3996 of 4619 relevant lines covered (86.51%)

0.98 hits per line

Jobs
ID Job ID Ran Files Coverage
1 29112811310.1 38
86.51
 GitHub Action Run
Source Files on build 29112811310