• Home
  • Features
  • Pricing
  • Docs
  • Announcements
  • Sign In

nickg / nvc / 26975615156
92%
master: 92%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 04 Jun 2026 08:02PM UTC
Jobs 1
Files 104
Run time 1min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst

04 Jun 2026 07:49PM UTC coverage: 92.286% (+0.001%) from 92.285%
26975615156

Pull #1513

github

web-flow
Merge 607420213 into 7b8792ea7
Pull Request #1513: Verilog: Support default values on macro functions

6 of 6 new or added lines in 1 file covered. (100.0%)

79013 of 85618 relevant lines covered (92.29%)

642729.0 hits per line

Jobs
ID Job ID Ran Files Coverage
1 26975615156.1 04 Jun 2026 08:02PM UTC 104
92.29
GitHub Action Run
Source Files on build 26975615156
  • Tree
  • List 104
  • Changed 1
  • Source Changed 0
  • Coverage Changed 1
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
  • Back to Repo
  • Pull Request #1513
  • PR Base - master (#26869778940)
STATUS · Troubleshooting · Open an Issue · Sales · Support · CAREERS · ENTERPRISE · START FREE · SCHEDULE DEMO
ANNOUNCEMENTS · TWITTER · TOS & SLA · Supported CI Services · What's a CI service? · Automated Testing

© 2026 Coveralls, Inc