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nickg / nvc / 26869778940
92%

Build:
DEFAULT BRANCH: master
Ran 03 Jun 2026 07:32AM UTC
Jobs 1
Files 104
Run time 1min
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02 Jun 2026 08:14PM UTC coverage: 92.285% (+0.006%) from 92.279%
26869778940

push

github

nickg
Fix sign extension bugs with Verilog ** operator

9 of 9 new or added lines in 3 files covered. (100.0%)

155 existing lines in 3 files now uncovered.

79007 of 85612 relevant lines covered (92.28%)

642027.3 hits per line

Coverage Regressions

Lines Coverage ∆ File
124
93.93
0.02% src/vlog/vlog-lower.c
30
97.9
0.0% src/jit/jit-irgen.c
1
97.76
0.0% src/mir/mir-node.c
Jobs
ID Job ID Ran Files Coverage
1 26869778940.1 03 Jun 2026 07:32AM UTC 104
92.28
GitHub Action Run
Source Files on build 26869778940
  • Tree
  • List 104
  • Changed 4
  • Source Changed 0
  • Coverage Changed 4
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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