nickg / nvc / 26395823927
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 103
Run time 1min
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Rst
coverage: 92.265% (-0.004%) from 92.269%
26395823927

push

github

nickg 
Improve checking for Verilog constant expressions

78 of 87 new or added lines in 5 files covered. (89.66%)

246 existing lines in 8 files now uncovered.

78777 of 85381 relevant lines covered (92.27%)

630338.01 hits per line

Uncovered Changes

Lines Coverage ∆ File
9
95.88
 -0.88% src/vlog/vlog-sem.c

Coverage Regressions

Lines Coverage ∆ File
122
95.82
 0.0% src/vlog/vlog-parse.c
73
93.51
 0.0% src/vlog/vlog-lower.c
21
87.98
 0.0% src/vlog/vlog-util.c
17
95.88
 -0.88% src/vlog/vlog-sem.c
5
96.28
 1.3% src/vlog/vlog-node.c
4
86.77
 0.0% src/vlog/vlog-dump.c
2
88.71
 -0.41% src/hash.c
2
76.11
 0.0% src/vlog/vlog-trans.c
Jobs
ID Job ID Ran Files Coverage
1 26395823927.1 103
92.27
 GitHub Action Run
Source Files on build 26395823927