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feat(api): expose HW SHA microbench result via /api/info (TA-339) (#304)

* feat(api): expose HW SHA microbench result via /api/info (TA-339)

- mining.c: cache us_per_op + khs_ceiling set by sha256_hw_microbench
- routes.c: surface as sha_us_per_op + sha_khs_ceiling in /api/info
- absent on boards without HW SHA microbench (D0/DPORT until follow-up)

Lets TA-320 optimization experiments compare against the per-device
peripheral ceiling via API instead of boot-log scrape.

* fix(mining): gate HW SHA boot probes to non-ASIC boards (TA-339 followup)

Bitaxe boards mine via the BM13xx ASIC, not the S3 HW SHA peripheral.
Reporting an "kH/s peripheral ceiling" derived from the AHB SHA on those
boards is misleading — it has nothing to do with the actual hashrate
ceiling (which is ASIC-bound at ~1.3-1.6 TH/s).

Gate sha256_hw_verify_text_preserved() and sha256_hw_microbench() at
boot by !ASIC_CHIP so the probes only run on dongles that actually use
the HW SHA peripheral for mining. /api/info will omit the
sha_us_per_op / sha_khs_ceiling fields on bitaxe as a result.

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