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feat: ASIC telemetry — single-chip dispatch fix + baseline defaults + diagnostics (#160)

closes the investigation thread kicked off in #158 after we saw the 601
reporting 0% HW error while AxeOS on identical silicon reported 0.08%.
root cause turned out to be a measurement bug, not a silicon win.

1. fix: chip index dispatch broken on single-chip boards
   asic_task cmd-response dispatch computed:
       uint8_t addr_interval = 256 / BOARD_ASIC_COUNT;
   on single-chip (601, 403) 256/1=256 wraps uint8_t to 0, and the
   subsequent asic_addr / 0 is undefined — silently discarded every
   cmd response, so TOTAL/ERROR/DOMAIN register reads never updated
   state. /api/stats showed null rates and zero raw counters, which
   read as "doing better than AxeOS" but was actually "reading nothing."
   650 dodged it because 256/2=128 fits. widened to uint16_t.

2. tune: set 601/650 defaults to AxeOS baseline (525/1150 and 400/1150)
   the 490/1100 we landed during 650 bringup was a conservative choice.
   AxeOS field data shows both boards run clean at stock voltages:
   - 601: 525 MHz / 1150 mV (BM1370 standard)
   - 650: 400 MHz / 1150 mV (BM1370XP for Gamma Duo)

3. diag: tps546 freq/oc readback + per-chip raw counter log
   readback of FREQUENCY_SWITCH and IOUT_OC_FAULT_LIMIT at end of
   tps546_init confirms our writes stick (they do). per-chip raw
   TOTAL_COUNT/ERROR_COUNT emitted in the 30s asic status tick plus
   exposed on /api/stats.asic_chips[] for board-to-board comparison
   without serial.

4. diag: subtract warmup baseline from raw total_raw/error_raw
   the BM1370 counters start from chip power-on, so the ~7.5-10s PLL
   ramp pollutes any session-cumulative ratio. record the first poll
   value as baseline; report current - baseline on /api/stats and in
   the log. cumulative ratios now track the delta-derived rate.

refs TA-198.

Co-authored-by: Claude Opus 4.7 <noreply@anthropic.com>

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